IC解密VERILONG串口单秒发数据
| IC解密 |
| /*+++++++TOP++++++++++++*/ module uart_tx( input wire sclk, input wire rst_n, output reg uart_tx ); parameter CLK_FREQ =24000000; //时钟频率50M parameter UART_BAUD = 115200; //时钟频率50M parameter MAX_BIT_COUNT = 31; //时钟频率50M localparam MAX_BAUD_CNT = CLK_FREQ / UART_BAUD;//434 reg [7:0] write_data; //发送数据 //运行计数器 reg [31:0] run_cnt; //波特率计数器 always @(posedge sclk or negedge rst_n) begin if(rst_n == 1'b0) run_cnt <= 32'd0; else if(run_cnt == CLK_FREQ) run_cnt <= 0; else run_cnt <= run_cnt + 1; end //波特率计数器 reg [8:0] baud_cnt; //波特率计数器 reg en_baud_cnt; //波特率计数器开关 always @(posedge sclk or negedge rst_n) begin if(rst_n == 1'b0) baud_cnt <= 8'd0; else if(en_baud_cnt == 1'b1) begin if(baud_cnt == MAX_BAUD_CNT) baud_cnt <= 8'd0; else baud_cnt <= baud_cnt + 1; end else baud_cnt <= baud_cnt; end //发送位计数器 reg [4:0] bit_cnt = 0; //波特率计数器 always @(posedge sclk or negedge rst_n) begin if(rst_n == 1'b0) bit_cnt <= 4'd0; else if(baud_cnt == MAX_BAUD_CNT) begin if(bit_cnt == MAX_BIT_COUNT) bit_cnt <= 4'd0; else bit_cnt <= bit_cnt + 1; end else bit_cnt <= bit_cnt; end |
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