芯片破解CPLD设计PID控制器
- 芯片破解timescale 1ns/100ps//时间尺度
- 芯片破解module pidctrl3 (
- isetpoint, // desire quater period 期望四分之一周期
- ifeedback, // quater period measured 四分之一周期测量
- iupdate,
- iclk,
- irst,
- ikp,
- iki,
- ikd,
- isynvalue,
- iscale,
- ilimit,
- ierrlimit,
- oreferr,
- oresult, // oresultput flux/strength溢出/强度
- ordy
- );
- 芯片破解input [15:0] isetpoint;
- input [15:0] ifeedback;
- input iupdate;
- input iclk;
- input irst;
- input [15:0] ikp;
- input [15:0] iki;
- input [15:0] ikd;
- input [15:0] isynvalue;
- input [11:0] iscale;
- input [15:0] ilimit;
- input [15:0] ierrlimit;
- output [15:0] oreferr;
- output [15:0] oresult;
- output ordy;
- reg [15:0] mula;
- reg [15:0] mulb;
- wire [30:0] mulc;
- reg [30:0] mulcq;
- reg [38:0] accq;
- wire [39:0] acc;
- reg [27:0] integralq;
- reg ordy;
- reg [7:0] statq;
- reg [15:0] errq;
- wire [16:0] tmperr;
- wire [16:0] tmperrabs;
- reg [15:0] derivq;
- wire chklimit;
- reg [45:0] delta;
- reg [45:0] deltaq;
- reg [47:0] deltasumq;
- wire [38:0] satdeltasum;
- wire [15:0] saterr;
- reg [15:0] saterrq;
- wire [15:0] effectiveerr;
- reg [38:0] satacc;
- reg [3:0] selscale;
- wire [15:0] fixresult;
- wire [15:0] absresult;
- reg [15:0] oresult;
- wire oversat;
- assign tmperr = {isetpoint[15],isetpoint} - {ifeedback[15],ifeedback};
- assign tmperrabs = tmperr[16] ? ~tmperr : tmperr;
- assign oversat = tmperrabs > {ierrlimit[15],ierrlimit};
- assign saterr = tmperr[16] ? (oversat ? ~ierrlimit : tmperr[15:0]) :
- (oversat ? ierrlimit : tmperr[15:0]);
- // always @(*)
- // case (err[16:15])
- // 2'b01 : saterr = 16'h7fff;
- // 2'b10 : saterr = 16'h8001;
- // default : saterr = err[15:0];
- // endcase
- always @(posedge iclk)
- if (irst) saterrq <= 'h0;
- else saterrq <= iupdate ? saterr : saterrq;
- //##################################################################
- always @(posedge iclk)
- if (irst) begin
- errq <= 'h0; // it records errors between feedbacks and targets
- derivq <= 'h0; // it records the changes of errq
- end else begin
- errq <= statq[0] ? saterrq : errq;
- derivq <= statq[0] ? saterrq - errq : derivq;
- end
- //##################################################################
- always @(*) // To save the number mulipliers, one single multiplier is time-multiplexed
- case (statq[3:1])
- 3'b001 : begin mula = errq; mulb = ikp; end // perform PID, proportional calculation
- 3'b010 : begin mula = integralq[27:12]; mulb = iki; end // perform PID, integral calculation
- 3'b100 : begin mula = derivq; mulb = ikd; end // perform PID, derivative calculation
- default : begin mula = 'h0; mulb = 'h0; end
- endcase
- assign mulc = {{15{mula[15]}},mula} * {{15{mulb[15]}},mulb};
- always @(posedge iclk)
- if (irst) integralq <= 'h0; // it records the sum of recent errq
- else integralq <= statq[1] ? integralq + {{12{errq[15]}},errq} - {{12{integralq[27]}},integralq[27:12]} : integralq;
- // ##################################################
芯片解密
